The present invention relates to a method of manufacturing a semiconductor device including a memory region and a logic circuit region, particularly to a method of manufacturing a semiconductor device having two charge storage regions for each word gate in a non-volatile memory device formed in the memory region.
As one type of non-volatile semiconductor memory device, a MONOS (Metal Oxide Nitride Oxide Semiconductor) or SONOS (Silicon Oxide Nitride Oxide Silicon) memory device is known. In the MONOS or SONOS memory device, a gate insulating layer between the channel region and the control gate is formed of a multi-layer stack of a silicon oxide layer and a silicon nitride layer, and charge is trapped in the silicon nitride layer.
A device shown in FIG. 16 is known as an example of this MONOS type of non-volatile semiconductor memory device (disclosed by Y. Hayashi, et al, in 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123).
In a memory cell 100 of this MONOS type, a word gate 14 is formed on a semiconductor substrate 10 through a first gate insulating layer 12. A first control gate 20 and a second control gate 30 formed in a side wall shape are respectively arranged on both sides of the word gate 14. A second gate insulating layer 22 exists between the bottom portion of the first control gate 20 and the semiconductor substrate 10. An insulating layer 24 exists between the side surface of the first control gate 20 and the word gate 14. Similarly, the second gate insulating layer 22 exists between the bottom portion of the second control gate 30 and the semiconductor substrate 10. The insulating layer 24 exists between the side surface of the second control gate 30 and the word gate 14. Impurity regions 16, 18 constituting a source region or a drain region are formed in the semiconductor substrate 10 between the opposed control gates 20 and 30 of adjacent memory cells.
Thus, one memory cell 100 has two MONOS type memory elements on the both sides of the word gate 14. The operations of these two MONOS type memory elements are independently controlled. Accordingly, one memory cell 100 can store information of two bits.
The present invention may provide a method of manufacturing a semiconductor device including a MONOS type non-volatile memory device having two charge storage regions, in which a memory region including a MONOS memory cell and a logic circuit region including a peripheral circuit of the memory or the like are formed on the same substrate.
According to the present invention, there is provided a method of manufacturing a semiconductor device having a memory region which includes a non-volatile memory device and a logic circuit region which includes a peripheral circuit of the non-volatile memory device. The method includes the steps of:
forming a first insulating layer above a semiconductor layer;
forming a first conductive layer above the first insulating layer;
forming a stopper layer above the first conductive layer;
patterning the stopper layer and the first conductive layer within the memory region;
forming an ONO film at least above the semiconductor layer and on both sides of the first conductive layer;
forming a second conductive layer at least on the entire surface of the memory region;
forming a side-wall shaped control gate at least on both sides of the first conductive layer within the memory region with the ONO film interposed, by anisotropically etching the second conductive layer;
removing the stopper layer within the logic circuit region;
pattering the first conductive layer within the logic circuit region to form a gate electrode of an insulated-gate field effect transistor in the logic circuit region;
forming a side-wall insulating layer at least on both sides of the gate electrode;
forming a first impurity layer as a source or drain region of the non-volatile memory device, and a second impurity layer as a source or drain region of the insulated-gate field effect transistor;
forming a silicide layer on the first impurity layer, the second impurity layer and the gate electrode;
forming a second insulating layer over the memory region and the logic circuit region;
polishing the second insulating layer such that the stopper layer within the memory region is exposed and the gate electrode within the logic circuit region is not exposed;
removing the stopper layer within the memory region; and
patterning the first conductive layer within the memory region to provide word gates of the non-volatile memory device in the memory region.